Computer systems commonly employ a bus to provide a data path connecting the elements of the system. Computer system elements, such as processors, memory modules and mass storage devices, are typically all coupled to the bus, so that bus signals are available to all such elements. In a common implementation, each element is assigned a particular address so that only bus communications addressing a particular element are received by that element. Buses of the type thus described are oftentimes parallel in nature, such as when many bits comprising a data word are carried over the bus simultaneously via a plurality of lines. Such busses are typically governed by a single clock so that all bus cycles are synchronous with that clock.
In the development, configuration and servicing of computer systems having a bus as set forth above, it is often necessary to study and analyze a sequence of bus cycles for such purposes as debugging, fine tuning system parameters and trouble-shooting. To capture a sequence of bus cycles, it has heretofore been necessary to utilize a test apparatus such as a logic analyzer or some other hardware attachable to the bus and dedicated to performing testing and monitoring functions. While such test equipment is capable of capturing a sequence of real-time bus cycles, it typically suffers from shortcomings in terms of performance in that the number of sequential cycles that is capturable is relatively small.
For instance, a high speed logic analyzer may be capable of capturing on the order of 65,000 consecutive bus cycles. Though such a number of captured cycles may suffice for purposes of analysis, with a bus cycle frequency of 16 MHz, as commonly used, it amounts to only four milliseconds of captured real-time bus cycle activity usable for analysis. With a relatively small capacity for captured cycles, it is crucial, with such test equipment, that the triggering conditions be precisely set. If the triggering conditions are not carefully evaluated and selected, it is highly likely that the bus event of interest will be outside the relatively narrow window of captured cycles. Furthermore, certain complex, intermittent system problems may be simply unsolvable with a device having a low capacity for captured cycles, because analyzing an extensive history of bus cycle information may be the only way to solve such problems.
Using dedicated test equipment to capture bus cycles has other drawbacks in terms of convenience and cost. Logic analyzers and other similar test apparatus are complex and costly pieces of hardware. Clearly, the aforementioned performance shortcomings are solvable by creating a logic analyzer with enormous memory capability. That, however, would make an already costly apparatus prohibitively expensive. Dedicated equipment for capturing bus cycles is often inconvenient to use as well, especially when performing service on computer systems in the field, where the test equipment must be physically brought to and connected to the bus. Furthermore, incorporating such a dedicated device in a computer system, aside from the cost, causes significant problems such as providing physical space for it and providing power for it.